Electronic Packaging & SMT

Cooling does not begin at the heat sink. It begins inside the package, where the die, interfaces, interconnects, and board determine how heat reaches the rest of the system.

Electronic packaging provides electrical connections, mechanical support, and protection for the silicon. Surface-mount technology (SMT) is the process of assembling components onto the surface of a printed circuit board (PCB). Their thermal behavior is linked, but package construction and board assembly are not the same thing.

1. Follow the heat paths

Heat can leave a device through its top surface, through the board, and through its other exposed surfaces. The fraction taking each route depends on the package, PCB stack-up, mounting interfaces, and cooling boundary conditions. Treating every physical layer as one series resistance misses these parallel paths.

A lidded flip-chip BGA is one example, not a universal package stack. An exposed-pad QFN may rely much more strongly on heat transfer into the PCB.

A top-side cooler needs a continuous path through the die-to-lid interface, lid, external thermal interface material (TIM), and cooler. On the board side, heat must spread from the package into copper and ultimately reach air, a chassis, or another cooling surface. A copper plane spreads heat; it is not, by itself, a heat sink to a fixed temperature.

2. Understand the package types

BGA, LGA, and QFN describe package connection formats. Flip-chip and wire bonding describe how a die is interconnected inside a package. For example, a BGA package can contain either a flip-chip or wire-bonded die.

Package and interconnect choices: what changes for thermal design
Type	What it means	What to check
BGA	Ball grid array: solder balls join package lands to the PCB.	Top-side versus board-side cooling, substrate spreading, ball layout, and solder-joint fatigue. Hidden joints often need X-ray inspection.
LGA	Land grid array: flat package lands mate to a socket or are soldered to a board, depending on the device.	Do not assume every LGA is socketed. For socketed devices, check retention loads, board deflection, and the supplier's mechanical limits.
QFN / DFN	Quad / dual flat no-lead packages use underside terminations; many include an exposed pad.	Exposed-pad attachment, solder coverage, and PCB copper/vias can strongly affect the heat path. Follow the specified pad's electrical connection.
Flip-chip	The die's active face connects to a substrate or interposer through bumps or pillars.	Bump geometry, underfill, die-backside cooling, and expansion mismatch. The interconnect process depends on the package generation.
Wire-bonded die	Fine wires connect die pads to a leadframe or substrate.	Die attach, paddle/substrate construction, and mold compound often matter more thermally than the fine bond wires.

3. From solder paste to assembled board

SMT assembly quality can change the thermal path even when the CAD geometry is unchanged. A typical reflow-based process includes:

Prepare and verify. Confirm the land pattern, board finish, component orientation, solder paste, and moisture-sensitive handling requirements. Use the component supplier's assembly guidance.
Print solder paste. Stencil thickness and aperture geometry set the deposited volume. Segmented apertures on large exposed pads can help control solder distribution and process behavior; the pattern is package-specific.
Inspect and place. Solder-paste inspection checks the deposit before pick-and-place positions the components. Paste volume, placement accuracy, and package coplanarity affect joint formation.
Reflow. Develop a profile for the actual board, paste alloy, and component limits. Thermocouples on representative locations reveal differences between small parts and high-thermal-mass areas. There is no single peak temperature or soak time suitable for every assembly.
Inspect and verify. Automated optical inspection checks visible features; X-ray helps inspect hidden solder joints and voids. Electrical testing checks function, while thermal testing evaluates whether the cooling path performs as intended.

4. Design the board-side heat path

Copper spreading and thermal vias

PCB copper conducts heat much more effectively than the surrounding laminate. Connected copper regions and thermal vias can carry heat from an exposed pad into internal or backside planes. Their benefit depends on where the heat can go next: a small enclosed board with little airflow may still run hot.

Vias are not all solid copper cylinders. For a conventional plated through-hole, the copper barrel is a thin annulus. Its axial conduction area is approximately π(D_outer² − D_inner²)/4, not the area of the entire hole.
Filled does not necessarily mean copper-filled. Resin fill and copper fill have different thermal properties. Use the actual construction, plating thickness, and connected layer geometry in a model.
Via-in-pad is also an assembly decision. Open holes can wick solder from the joint. Discuss filling, capping, tenting, and stencil design with the board fabricator and assembler; follow package-specific recommendations.
Thermal and electrical needs interact. Clearances, isolated nets, thermal-relief spokes, and copper discontinuities can restrict spreading. Never connect an exposed pad to an arbitrary plane just because it improves a thermal model.

Underfill, die attach, and contact

Underfill helps redistribute mechanical stresses around die interconnects, but its conductivity, coefficient of thermal expansion (CTE), modulus, and adhesion all matter. It is not automatically a high-performance thermal interface. Likewise, a thin bond line is useful only if the assembly still achieves adequate coverage, contact, and reliability.

5. Work through a resistance estimate

For uniform, one-dimensional conduction through a layer:

R_cond = t / (kA) [K/W]
ΔT = Q_path R_cond

Here, t is thickness in meters, k is thermal conductivity in W/(m·K), and A is conduction area in m². Q_path is the heat passing through that layer, not automatically the device's total dissipation.

Illustrative exposed-pad solder layer

Assume a 5 mm × 5 mm solder contact, a 75 µm bond-line thickness, k = 50 W/(m·K), and 10 W passing through the joint. These are example inputs, not a material specification or assembly recommendation.

A = 25 × 10⁻⁶ m²
R = (75 × 10⁻⁶) / (50 × 25 × 10⁻⁶)
R = 0.060 K/W
ΔT = 10 × 0.060 = 0.60 K

If a simplified model treats 20% of the area as completely nonconducting, A_effective = 0.8A. The estimated resistance becomes 0.075 K/W, and the temperature rise becomes 0.75 K.

Limit of this estimate: it ignores spreading, contact resistance, nonuniform heat flux, and the actual shape of voids. It is an area-loss sensitivity calculation, not a solder-void acceptance rule. The complete package and PCB can contribute much more resistance than this single layer.

6. Read thermal metrics correctly

Datasheet thermal numbers only make sense with their test conditions. TI's thermal-metrics guide distinguishes thermal resistances from characterization parameters and explains why board and boundary conditions matter. [1]

θ_JA, junction-to-ambient: reflects a device on a specified test board in a specified environment. It is not an intrinsic package constant that can be transferred unchanged to a different PCB or enclosure.
θ_JC, junction-to-case: is measured with a controlled heat path to a specified case surface. Check whether the reported value refers to the top or bottom and whether the real cooling arrangement resembles that condition.
ψ_JT, junction-to-top characterization parameter: relates junction temperature to measured package-top temperature using total device power. It is not a pure thermal resistance because heat leaves by other routes too.

T_j ≈ T_top + ψ_JT P_device

Use that estimate only with a compatible characterization condition and the specified top-surface measurement location. An infrared camera needs appropriate emissivity treatment; a thermocouple's attachment can disturb a small package's temperature. Neither directly measures an internal junction hot spot.

7. Connect temperature to reliability

Silicon, organic substrates, solder, copper, and PCB laminates expand differently. Temperature changes therefore create differential displacement. A first-order free-expansion estimate is:

ΔL_mismatch ≈ (α₁ − α₂) L ΔT

This explains why CTE mismatch, temperature swing, and distance from a package's neutral point matter. It is not a solder-fatigue life model: real joints experience constraint, creep, plastic deformation, and a time-dependent temperature history.

Thermal cycling: evaluate solder fatigue, interfacial delamination, and changes in thermal contact under relevant cycle ranges, dwell times, and ramp rates.
Warpage and mounting: package/board bending can affect joint formation during reflow and cooler contact during operation. Cooler preload must remain within device and board limits.
Moisture and reflow: follow moisture-sensitivity handling and storage instructions. Absorbed moisture can contribute to package damage during heating.
Failure investigation: compare electrical symptoms, measured temperature changes, inspection images, and, when appropriate, cross-sections rather than attributing every failure to overheating.

8. Think beyond a single die

In 2.5D packaging, dies sit side by side on an interposer or connect through a bridge structure. In 3D packaging, dies are stacked vertically. Both can create thermal coupling: one die's temperature depends on its neighbors' power as well as its own.

A single average package power is often insufficient for a useful model. Start with a per-die power map, die dimensions, interface properties, and realistic cooling boundaries. Consider heat spreading through the lid, constrained heat-removal routes from buried dies, and different allowable temperatures for logic and memory.

More detailed simulation is useful only when its assumptions are credible. Correlate the model with measurements, account for sensor location and uncertainty, and examine multiple workloads rather than tuning to one operating point. The external cold plate or heat sink remains part of that coupled system.

9. A practical design-review checklist

Inputs: power per device/die, operating and transient loads, temperature limits, ambient/coolant conditions, and manufacturing tolerances.
Package: cross-section, dominant heat paths, interface properties, supplier thermal-model guidance, and mechanical loading limits.
Board: stack-up, copper connectivity, thermal-via construction, available spreading area, and the eventual heat-rejection surface.
Assembly: land pattern, stencil, paste, moisture controls, measured reflow profile, and inspection/acceptance criteria agreed with manufacturing.
Validation: defined sensor locations, calibrated instruments, measurement uncertainty, repeatability, and model-to-test comparisons over relevant conditions.
Reliability: thermal cycling, board strain, mounting loads, and inspection of interfaces after representative stresses.

10. References and further reading

Texas Instruments: Semiconductor and IC Package Thermal Metrics (SPRA953, PDF) — interpretation and limitations of package thermal metrics.
NXP: Assembly guidelines for QFN and SON packages (AN1902, PDF) — board design, solder-paste printing, reflow, and inspection. Apply its guidance within its stated package scope.

Use the current datasheet and assembly guidance for the specific device alongside these general references. The illustrations and worked example here are educational, not a qualified product design.